-Impossible to quantify unless you can tweak the actual jitter specs in the same DAC/cdp.
-If a designer has taken the road less travelled in reducing jitter to minimal levels other areas of the DAC/CDP (power supply, filtering, analog section, isolation) are highly likely to be well thought out and complementary.
Dgarretson, I assume you did this test and only changed the clock to a low jitter clock circuit, while leaving any other component unchanged. If so how did you do this? did you actually measure clock skew and spectral analysis pre/post or toss in a super clock look at the marketing specs and just go for it?
-If a designer has taken the road less travelled in reducing jitter to minimal levels other areas of the DAC/CDP (power supply, filtering, analog section, isolation) are highly likely to be well thought out and complementary.
Dgarretson, I assume you did this test and only changed the clock to a low jitter clock circuit, while leaving any other component unchanged. If so how did you do this? did you actually measure clock skew and spectral analysis pre/post or toss in a super clock look at the marketing specs and just go for it?